At the Embedded World Show in Nuremberg, Germany, Lattice Semiconductor demonstrated a camera supporting the Panasonic MN340411080p image sensor using the LatticeECP3. The Panasonic MN34041 sensor is mounted on the front panel to match the lens and is integrated with Lattice's HDR-60 camera development kit. The sensor fully supports a color image signal processing (ISP) pipeline of 60 frames per second using the LatticeECP3TM FPGA in the Lattice HDR-60 kit.
The hardware is designed to support the full 1080p resolution of the Panasonic MN34041 sensor and is implemented in FPGA with 60fps stream mode, requiring no external frame buffering. The integrated image signal processing IP pipeline provides end-to-end ISP support, from sensors to display images, and includes a sensor interface, defective pixel correction, and 2D noise reduction. Other features include a high-quality DeBayer color correction matrix, fast auto exposure, auto white balance, gamma correction, and character and graphics overlays. Lattice's HDMI PHY IP can output information to the HDMI/DVI monitor.
“Designers of high-quality video applications are very pleased with the ability of our FPGA LatticeECP3 family to support Panasonic 1080p,†said Niladri Roy, Senior Manager, Lattice Vertical Markets. “Our end-to-end, sensor-to-display FPGA-based The video image signal processing architecture provides image signal processing IP, supports 1080p sensors, and the design kit makes the design of high-quality, low-power, low-cost cameras more convenient and rapid."
The hardware is designed to support the full 1080p resolution of the Panasonic MN34041 sensor and is implemented in FPGA with 60fps stream mode, requiring no external frame buffering. The integrated image signal processing IP pipeline provides end-to-end ISP support, from sensors to display images, and includes a sensor interface, defective pixel correction, and 2D noise reduction. Other features include a high-quality DeBayer color correction matrix, fast auto exposure, auto white balance, gamma correction, and character and graphics overlays. Lattice's HDMI PHY IP can output information to the HDMI/DVI monitor.
“Designers of high-quality video applications are very pleased with the ability of our FPGA LatticeECP3 family to support Panasonic 1080p,†said Niladri Roy, Senior Manager, Lattice Vertical Markets. “Our end-to-end, sensor-to-display FPGA-based The video image signal processing architecture provides image signal processing IP, supports 1080p sensors, and the design kit makes the design of high-quality, low-power, low-cost cameras more convenient and rapid."
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