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Abstract: In combination with the design of a TV tracking system, the internal integrated integrated video port is introduced, and its implementation method of seamless connection with encoder/decoder is studied, including its driver composition and CCS development environment. The package form focuses on the general implementation of the acquisition, processing and display of standard PAL video signals.Keywords: TV tracking; DM642; video port; driver In modern air defense fire control system, searching, discovering and tracking target is the working basis of the whole system. The most important detection and reconnaissance means is still radar, but it is a The electromagnetic wave source, while acquiring the target information, also exposes itself, is vulnerable to attack by anti-radiation missiles, and it cannot track low-altitude targets, and there are effects such as lobes, multipath effects, and ground object interference, which is serious. Affects the normal functioning of its functions.
The TV tracking system uses the high-precision camera to acquire the target scene information, converts it into a video signal and sends it to the monitor, and guides (also can be guided by the radar) the servo platform to make the target enter the capture window, and capture and detect the target in real time. The pitch and azimuth error signals of the target relative to the optical axis are obtained, and the motion of the servo platform is controlled to achieve tracking of the target. The TV tracking system has the advantages of high resolution, visible image, good anti-interference performance and low cost. It has received universal attention in the military and has become a powerful complement to the radar in the air defense fire control system.
DSP has been widely used in the field of video and image processing, especially in embedded systems. DM642 (DigitalMedia) is a high-performance fixed-point DSP chip for video/image processing introduced by TI in 2003. Compared with the previous C64x, its frequency is 500-600MHz, up to 720MHz, and the instruction execution speed is up to 4,000~4 800. M IPS, the instruction set is fully compatible with C64X. In particular, it has 3 independently configurable video ports that can be independently configured as video capture or display ports, all supporting multiple capture/display schemes and video standards, supporting RAW video sets, and can be implemented with general video encoders/decoders. The seamless connection, and the video signal can be quickly transferred between the memory and the video port by means of EDMA.
System principle and design
Most of the functions of TV tracking systems in early or active weapon systems in various countries are realized by hardware circuits. The structure is complex, the requirements on environmental conditions are high, and the implementation of complex search and tracking algorithms is seriously hindered. The search and tracking capabilities are low, especially It is not suitable for modern air raids in all airspace and multiple levels. With the development of digital technology and graphic image processing technology, the TV tracking system is also developing in the direction of digitization, as shown in Figure 1.
The digital TV tracking system adopts an advanced DSP digital processor and applies modular design ideas. Not only is the overall design modularized, but also the modularization of the system hardware and software design. The whole system is divided into six functional modules on the hardware: image acquisition module, target tracking and identification module, communication control module, servo control module, character and information superimposition module and power module; software can be divided into image acquisition module and image. Processing module, identification tracking module, display control module, and main control module.
The main processing work of the TV tracking system is completed by the core processing board. The processing chip adopts TMS320DM642 DSP. Its remarkable feature is the integrated video input and output port, which is connected to the peripheral video encoding/decoding chip respectively. The decoding chip collects the TV signal through the CCD. After the number conversion, the tracking algorithm is processed to obtain the offset of the target centroid to the center of the field of view, and sent to the servo control module to drive the pan-tilt rotation to realize automatic tracking. The communication control module accepts the fire control system parameter signal output by the fire control computer, and completes superposition with the video signal by the DSP control. The specific superimposed signals include the target height amount, the distance amount and the speed amount, and the field center cross line. The system design uses an FPGA located between the DSP and the video coding chip to complete the superposition function, since this part of the circuit is more focused on the FPGA. The function is implemented, so the specific design is not detailed in this article.
DM642 video port hardware design
This system combines the characteristics of DM642, and uses two video ports to connect video decoding chip and video coding chip (FIA company's SAA7115 and SAA7105H), directly build video capture and display channels, and program the encoder/decoder chip through I 2 C bus. Make settings, specific technology can query related websites, this article focuses on the design ideas of this system.
Figure 2 video capture and display main hardware circuit
Figure 2 is the main hardware circuit of the video acquisition and display of this system. Since the DM642 itself is designed for video/image processing, its internal highly integrated video acquisition unit and display unit support the mainstream codec chip, which effectively simplifies the peripheral circuit. What needs to be explained here is:
1) The video data input of this system adopts color PAL system, the output is black and white PAL system, the middle adopts YUV422 code, the data bit is 8 bits.
2) The video port 0 (Video Port0) of the DM642 and its supporting control signals are first subjected to signal holding and transceiving conversion circuits, and then connected to the corresponding pins of the decoding chip SAA7115. This system is applicable to all major standard synthetic video, and its internal registers are controlled by the I 2 C bus for function selection. The specific operation functions are packaged in the software driver part.
3) DM642's video port 2 (Video Port2) is used as a video display. This encoder can perform RGB, HD, NTSC, PAL encoding, and can also encode the S-Video by programming. Its programming is also done via the I 2 C bus.
4) Similar decoding circuit, DM642 video port 2 can be directly connected to the encoding chip, but the system code display circuit is connected to the DSP and encoder (Philp SAA7105) through an FPGA (XiL inx XC2S300E), on the one hand, the video signal is superimposed. Characters, gates and other information, on the other hand used to logically process various control signals, making full use of the FPGA space, avoiding additional logic control circuits.
5) The DM642 video port control signal and the codec chip control signal mainly have line synchronization, field synchronization and clock signal, especially to ensure the 33Ω matching resistance of the video signal.
Software design of DM642 video operation
Considering versatility and compatibility, the driver for the video port portion of the DM642 in this system is divided into two parts: a generic driver for the video port and a dedicated driver for the video processing peripheral. The former is fixed for the fixed model DSP, provided by TI company, the user does not need to change; the latter depends on the video peripherals designed by the user, generally only related to the peripheral hardware, and its related parameters and functions are encapsulated by the user. Both are connected by an extended device controller (EDC) inside the DSP, which is responsible for the collection, transmission and processing of video signals.
For TI's DSP development environment CCS, the above two-part driver can be further encapsulated into an FV ID (frame video) driver model, which serves as a general-purpose I/O model for video port operations, and mainly includes the following two types of functions. model:
1) The general-purpose driver part mainly completes the operations of reading and writing the video port of the DSP chip. Mainly divided into overall port configuration, single acquisition / display channel configuration, video port interrupt configuration, its parameter types are stored in the corresponding structure in Vport. h, VportCap. h, VportDis.h, Vport. h, user development The appropriate parameters can be selected in the program by referring to [1].
2) Dedicated driver part, the main task is the initialization operation and working mode selection of the video encoding/decoding chip. For example, if the system uses PHILP's SAA7105 and SAA7115 as video encoder/decoder, it needs to encode/decode the format and cache. Modes and other aspects are set, generally the configuration parameters are defined in the structure for the project to call, because the extended device controller encapsulates the universal driver part into a series of AP I interfaces, which can be called when the user writes the dedicated driver part, the main AP The I information is stored in EDC.h. For details, please refer to the TI website. The author focuses on the method of video signal acquisition and display in the DM642EVM. In order to complete the video stream establishment and management, the main work is shown in Figure 3.
Figure 3 Video signal flow establishment and management
1) Define the common attributes of the video port in the system configuration file (B IOS configuration file cdb), respectively establish the encoding channel and decoding channel as required, and specify the working parameters of each channel. For specific parameter types, see Vport Cap. h and Vport Dis. h .
2) Since the EVM has packaged the video peripheral driver (dedicated driver part) into the FV ID library, the user only needs to refer to the structure in saa7105.h, saa71105.h to establish parameter objects for each video peripheral (similar to VC++). The object in the class) to make it work in the selected mode.
3) In the CCS project execution function, set the trigger mode for video capture and display. Generally, the video capture uses the interrupt mode. When the buffer of the acquisition channel is saturated, an interrupt request is issued. The video display trigger is generally in the default mode.
4) In the response function, first switch its cache pointer to the alternate cache, and then process the current data area, in particular, for
In PAL video, the acquisition program automatically reorders the parity field pixels. The one-dimensional buffer data sequence directly corresponds to the pixel values ​​of the top left to the bottom right of the video. The single pixel value is a structure object, including all its color features. For easy reading of image processing functions. Then, the processing result is written into the buffer area of ​​the display channel. After the writing is completed, the buffer area of ​​the display channel is switched to the standby buffer. After the display task is started, the display encoding circuit automatically reads the buffer area and encodes and outputs according to the set mode.
Conclusion
TMS320DM642 is a high-performance fixed-point DSP chip for video/image processing. Its hardware design and software construction meet the special needs of video/image field. Its own and its subsequent models have a wide application prospect in this field. Combining the design of a TV tracking system, the author focuses on the principle and implementation of its video port related software and hardware, providing reference for software development and hardware circuit design for developing other video/image processing systems, especially the establishment of standard TV signal streams. The management method, after designing and debugging, successfully realized the acquisition, buffering, processing and display of standard standard television (PAL, NTSC). The experimental results prove that the method is feasible and the system runs stably.
The problem of the design of this system is that the optimization efficiency of the C compiler of the development environment is very low. Although the assembly language is difficult to write, the readability and maintainability are poor, but in order to ensure the execution speed of the complex processing algorithm, the next step is to Some core programs are written in assembly language.
references:
[ 1 ] Texas Insruments. TMS320DM642 video / imaging fixed - point digital signal p rocessor [ Z ]. Texas Insruments Incorporated, 2003.
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